A flip-chip ball grid array (FCBGA) semiconductor package is a package structure comprising both a flip chip and a ball grid array, wherein an active surface of at least one chip is electrically connected to a surface of a substrate via a plurality of solder bumps in a flip-chip manner, and a plurality of solder balls are implanted on an opposite surface of the substrate to serve as input/output (I/O) connections. This package structure yields significant advantages to effectively decrease the package size, reduce resistance and improve electrical performances without using conventional bonding wires, thereby preventing decay of signals during transmission. Therefore, the FCBGA semiconductor package has become a mainstream package product for chips and electronic elements of the next generation.
Referring to FIG. 10, the above FCBGA semiconductor package comprises a substrate 70; a chip 71 mounted on and electrically connected to an upper surface of the substrate 70 in a flip-chip manner; and a plurality of solder balls 72 implanted on a lower surface of the substrate 70 to be electrically connected to an external device. This package further comprises an encapsulant 73 formed on the upper surface of the substrate 70 by a molding process to encapsulate the chip 71. The related prior arts include U.S. Pat. Nos. 6,038,136, 6,444,498 and 6,699,731 and Taiwanese Patent No. 559960, which have disclosed similar package structures for improving the electrical performances of packages and satisfying the requirements for advanced electronic products.
However, the FCBGA semiconductor package still causes significant drawbacks in its fabrication processes. During the molding process of forming the encapsulant 73, in order to firmly fix the substrate 70 in an opening 77 of a substrate carrier 75 (as shown in FIG. 11) and prevent resin flashes on the substrate 70 as well as facilitate a subsequent mold-releasing process, the substrate 70 usually needs to be sized larger to have additional length and width. After the molding process is complete, extra portions in length and width of the substrate 70 are cut off according to a predetermined substrate size (for example, 31 mm×31 mm shown in FIG. 10) required for the semiconductor package. The discarded extra portions of the substrate 70 not only cause a material waste but also increase the material and fabrication costs.
Referring to FIG. 11, in U.S. Pat. No. 6,830,957, a clamping area a is extended from each side of the substrate 70, making the size of the substrate 70 larger than that of a mold cavity 81 of an encapsulating mold 80, such that the substrate 70 can be well clamped by the mold 80. As a result, the encapsulant 73 would not flash to the lower surface of the substrate 70 and not damage the bondability of ball pads 74 on the substrate 70 for implanting the solder balls 72. However, such design obviously increases the size of the substrate 70. For a single conventional package with the substrate 70 having the size of 31 mm×31 mm (as shown in FIG. 10), a distance of the clamping area a should be at least 0.6 mm to provide a good flash-preventing effect. Therefore, an additional portion of 1.2 mm that is to be eventually cut off is included respectively in the length and width of the substrate 70, which thus increases materials required for the substrate 70 and also increases the overall fabrication cost of the package (the substrate cost is generally more than 60% of the overall cost of the flip-chip package).
Furthermore, in accordance with the singulated package product shown in FIG. 10, the cost of the substrate 70 used in the molding process would further be increased. In order to successfully release the mold 80 when the molding process is complete, as shown in FIG. 12, a mold-releasing angle 82 is formed on an edge of the encapsulant 73 in contact with the substrate 70 by the shape of the mold cavity 81. Generally, the mold-releasing angle 82 should not be larger than 60° to provide a satisfactory mold-releasing effect. For a single package with the substrate 70 having the size of 31 mm×31 mm, an additional length or width b of at least 0.58 mm is required for the substrate 70 to accommodate the encapsulant 73 having the mold-releasing angle 82, such that an additional portion of 1.16 mm that is to be eventually cut off is included respectively in the length and width of the substrate 70, together with a cutting path c of 0.6 (0.3×2) mm respectively in the length and width of the substrate 70 reserved for a singulation process. Therefore, the size of the substrate 70 required during fabrication of the package is (31+1.2+1.16+0.6)mm×(31+1.2+1.16+0.6) mm, instead of 31 mm×31 mm. This causes not only a waste of utilization of the substrate but also 15˜20% increase in the overall cost.
The above problem leads to significant difficulty in the fabrication of the FCBGA semiconductor package. Although the molding process of forming the encapsulant 73 is an essential step for fabricating the package, it would effectively increase the size and material cost of the substrate 70 and is not advantageous for mass production. This thus sets a bottleneck in development of the FCBGA semiconductor package.
Therefore, the problem to be solved here is to provide a method for fabricating semiconductor packages, which can reduce the size and cost of a substrate, prevent resin flashes, and solve the mold-releasing problem, to satisfy requirements for mass production.